IBM, GlobalFoundries, and Samsung said Monday that they have found a way to make thinner transistors, which should enable them to pack 30 billion switches onto a microprocessor chip the size of a fingernail. The tech industry has been fueled for decades by the ability of chipmakers to shoehorn ever smaller, faster transistors into the chips that power laptops, servers, and mobile devices. But industry watchers have worried lately that technology was pushing the limits of Moore’s Law — a prediction made by Intel co-founder Gordon Moore in 1965 that computing power would double every two years as chips got more densely packed. From a report: Today’s chips are built with transistors whose dimensions measure 10 nanometers, which means about 1,000 fit end-to-end across the diameter of a human hair. The next generation will shrink that dimension to 7nm, and the IBM-Samsung development goes one generation beyond that to 5nm. That means transistors can be packed four times as densely on a chip compared with today’s technology. “A nanosheet-based 5nm chip will deliver performance and power, together with density,” said Huiming Bu, IBM’s director of silicon integration and device research. Take all those numbers with a nanograin of salt, though, because chipmakers no longer agree on what exactly they’re measuring about transistors. And there’s also a long road between this research announcement and actual commercial manufacturing. IBM believes this new process won’t cost any more than chips with today’s transistor designs, but its approach requires an expensive shift that chipmakers have put off for years: the use of extreme ultraviolet light to etch chip features onto silicon wafers.
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