Reader MojoKid writes: AMD has been talking about the claimed 40% IPC (Instructions Per Clock) improvement of its forthcoming Zen processor versus the company’s existing Excavator core for ages. Zen’s initial availability is slated for late this year, with lager-scale roll-out planned for early 2017. However, last night, at a private press event in San Francisco, AMD unveiled a lot more details on their Zen processor architecture. AMD claims to have achieved that 40 percent IPC uplift with a newly-designed, higher-performance branch prediction and a micro-op cache for more efficient issuing of operations. The instruction schedule windows have been increased by 75% and issue-width and execution resources have been increased by 50%. The end result of these changes is higher single-threaded performance, through better instruction level parallelism. Zen’s pre-fetcher is also vastly improved. There is 8MB of shared L3 cache on board now, a unified L2 cache for both instruction and data, and separate, low-latency L1 instruction and data caches. The new archicture offers up to 5x the cache bandwidth to the cores versus previous-gen offerings. However, after all the specsmanship was out of the way, AMD actually showcased a benchmark run of an 8-core Zen Summit Ridge procesor versus Intel’s Broadwell-E 8-core chip, both running at 3GHz and processing a Blender rending workload. In the demo, the 8-core Zen CPU actually outpaced Intel’s chip by a hair. Blender may have been chosen for a reason but this early benchmark demo looks impressive for AMD and its forthcoming Zen architecture.
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